CMOS static RAM cells are known to provide power advantages over a static RAM cell which uses polysilicon load resistors. Because the polysilicon load can be placed on top of the N channel transistors, static RAMs with polysilicon loads have been significantly more dense than designs with CMOS cells. CMOS cells have recently been developed which use the overlying polysilicon layer to form a P channel transistor, albeit, a relatively poor transistor in terms of its transconductance. This P channel device is then used as the load in place of the polysilicon resistor. This seemed to offer the potential of having both the power advantage of CMOS and the density advantage of polysilicon resistors for the loads.
A problem in this regard, however, is how to make good ohmic contact between polysilicon layers and to the source/drain N type regions in the substrate. The P channel polysilicon device is P type whereas, the underlying polysilicon layer which is used for gates of N channel devices in the cells, is N type. This underlying polysilicon layer is doped to N type both before and at the same time as the source/drains are doped. Consequently, bringing the upper P type polysilicon layer in contact with the underlying N type polysilicon layer and/or the N type source/drain region forms a PN junction instead of the needed ohmic contact. One technique to make this contact is to use an aluminum contact to the desired source/drain in the substrate. Both the P and N type polysilicon layers are also brought into contact with this aluminum, making ohmic contact thereto. Consequently, the ohmic contact is achieved by the P type layer, N type layer, and the source/drain region each being in ohmic contact with this aluminum. This type of contact has a significant detrimental affect on density. Because aluminum metal lines must be used extensively in the array for optimizing performance, the room required for an extra metal contact adversely affects cell density in a significant way.